This invention relates generally to arithmetic circuitry and more particularly, it relates to a complementary metal-oxide-semiconductor (CMOS) full adder circuit.
Heretofore, implementation of conventional CMOS full adder circuits have occupied a considerable amount of space area on the integrated circuit substrate. This problem is created by the high number of individual transistor elements and their lead interconnection space required in fabricating the adder circuits. Thus, these prior art adder circuits suffer from the disadvantages of slow speed of operation, high input capacitance and high manufacturing costs.
It would therefore be desirable to provide a CMOS full adder circuit which possesses an improved architecture and topological regularity of individual transistor elements so as to increase their circuit density and reduce their input capacitance when fabricated on an integrated circuit semiconductor chip. The full adder of the present invention is embodied in balanced CMOS devices which have a significantly reduced number of individual transistor elements over the conventional CMOS design, thereby permitting a reduced propagation delay and lower input capacitance.